With the shrinking of the semiconductor device design rules, the degree of circuit integration has improved dramatically, making it possible to include more than one hundred million field effect transistors (MISFETs) on a single chip. In order to realize such a chip, there is a demand not only for the development of microfabrication techniques such as lithography, etching, etc., with a process precision on the order of some tens of nanometers, but also for forming transistor structures separately suitable for n-channel MISFETs and p-channel MISFETs.
A conventional MISFET includes an inner side wall for adjusting the amount of offset (offset side wall) and an outer side wall for forming source and drain regions on the side surface of the gate electrode. With respect to an example where an offset side wall is formed, the formation method will be described briefly.
First, a gate electrode is formed on a semiconductor substrate, and then an insulating film such as a silicon oxide film is deposited across the entire wafer surface. Then, the entire wafer surface is etched back using a method such as dry etching to thereby form an offset side wall made of an insulator on a side surface of the gate electrode.
However, if an offset side wall is formed by a method described above, the width of the offset side wall will be the same between n-channel MISFETs and p-channel MISFETs. Typically, a source/drain extension implantation for an n-channel MISFET uses arsenic, which has a smaller thermal diffusion. On the other hand, a source/drain extension implantation for a p-channel MISFET uses boron, which thermally diffuses more easily. In the formation of a transistor, both the n-channel MISFET and the p-channel MISFET are simultaneously subjected to a heat treatment step such as an impurity activation annealing, and if the offset side wall is formed so as to suit the n-channel MISFET, for example, the width (thickness) will be small. With a small-width offset side wall used for the p-channel MISFET, boron diffuses across a wide area under the gate electrode, resulting in a large overlap between the gate electrode and the extension region, thus forming a transistor with its characteristics being significantly degraded due to the short-channel effect. On the other hand, if a thick offset side wall is formed so as to suit the p-channel MISFET, the n-channel MISFET will have a large ON resistance and the ON current will be degraded, due to the small amount of overlap between the gate electrode and the extension region.
For generations of relatively large gate lengths, the amount of overlap is relatively large, i.e., 10 nm or more, and the amount of overlap can be adjusted by adjusting the implantation dose of an impurity. However, for generations of very short gate lengths, e.g., 45 nm or 32 nm, it is required to adjust the amount of overlap on the order of nanometers, and it is therefore difficult to control the amount of overlap by merely adjusting the dose of the impurity to be implanted. Therefore, there is a demand for the formation of dual offset side walls in which the width can be optimized for each of the n-channel MISFET and the p-channel MISFET. Note that the “dual offset side walls” as used herein refer to side wall spacers that are used for adjusting the amount of offset of the diffusion layer in the extension region or the LDD region and that are provided separately for the p-channel MISFET and the n-channel MISFET.
A method for forming the dual offset side walls will be described with reference to FIGS. 8A to 8D (Patent Document 1). FIGS. 8A to 8D are diagrams showing a method for forming dual offset side walls according to a conventional example.
First, as shown in FIG. 8A, a first gate insulating film 1001a and a first gate electrode 1002a are formed on the n-channel MISFET formation region (left-hand portion of the figure) of a semiconductor substrate 1000, and a second gate insulating film 1001b and a second gate electrode 1002b are formed on the p-channel MISFET formation region (right-hand portion of the figure) of the semiconductor substrate 1000.
Then, as shown in FIG. 8B, an insulating film 1003, which is for forming an offset side wall made of a silicon oxide film, or the like, is deposited to a thickness of 10 nm across the entire surface of the semiconductor substrate 1000.
Then, as shown in FIG. 8C, with a resist mask 1004 over the p-channel MISFET formation region of the semiconductor substrate 1000, impurity ions 1005 of an impurity having a relatively large atomic weight such as arsenic are implanted across the entire surface of the semiconductor substrate 1000. In such a case, arsenic is implanted only into the insulating film 1003 on the n-channel MISFET formation region, and damages 1006 are introduced by the ion implantation into the insulating film 1003. The etching rate of a portion of the insulating film 1003 that has received the damages 1006 is higher than a portion that has not been damaged by the ion implantation. Therefore, the insulating film 1003 is thinned during an etch back 1007 and the subsequent washing step, resulting in a first offset side wall 1003a, which is thinner than a second offset side wall 1003b, formed on the side surface of the first gate electrode 1002a (see FIG. 8D).
Then, as shown in FIG. 8D, the insulating film 1003 is etched back after removing the resist mask 1004, thereby forming the first offset side wall 1003a and the second offset side wall 1003b thicker than the first offset side wall 1003a. Then, with the p-channel MISFET formation region covered by a resist, or the like, arsenic is ion-implanted into the n-channel MISFET formation region of the semiconductor substrate 1000 using the first gate electrode 1002a and the first offset side wall 1003a as a mask, thereby forming a first extension region 1010a. Then, with the n-channel MISFET formation region covered by a resist, or the like, boron is ion-implanted into the p-channel MISFET formation region of the semiconductor substrate 1000 using the second gate electrode 1002b and the second offset side wall 1003b as a mask, thereby forming a second extension region 1010b. 